The present invention relates to the field of multiplier circuits, and more particularly, to the field of four-quadrant analog multiplier circuits.
Analog multiplier circuits form important building blocks for devices such as adaptive filters, function generators, and modulators. In the emerging field of artificial neural networks, implementation of useful network structures in analog integrated circuitry will in many cases require large arrays of multipliers. Some designs for analog four-quadrant multiplication MOS circuitry existing to date are based upon the characteristics of MOS transistors in saturation. See Soo, D.C., and Meyer, R.G., ."A Four-Quadrant NMOS Analog Multiplier," IEEE J. Solid-State Circuits, vol. SC-17, pages 1174-1178, December 1982; and Bult, K., and Wallinga, H., "A CMOS Four-Quadrant Analog Multiplier", IEEE J. Solid-State Circuits, vol. SC-21, pages 430-435, June 1986. However, these circuits typically require twenty to forty transistors to provide a practical working circuit. Another type of four-quadrant multiplier circuit is taught in U.S. Pat. No. 4,071,777, "Four-Quadrant Multiplier" by Herrmann, Jan. 31, 1978. Herrmann's basic circuit includes two enhancement mode transistors and requires separate DC bias voltages applied to each of two transistor gates as well as voltage inputs representing the multiplicands, resulting in a complicated circuit.
Still another four-quadrant multiplier circuit is taught by Enomoto, J., et al., "Integrated MOS Four-Quadrant Analog Multiplier Using Switched Capacitor Technology For Analog Signal Processor IC's," IEEE Journal of Solid-State Circuits, Vol. SC-20, No. 4, August 1985. Enomoto teaches the use of two enhancement mode transistors biased in the linear or triode region in combination with a difference amplifier to perform four-quadrant multiplication. However, this device disadvantageously requires circuitry to compute the difference in currents flowing through the two transistors.
Therefore, a need exists for a four-quadrant multiplier having a minimal number of transistors and which does not require application of bias voltages to each transistor gate or inclusion of amplifiers within the circuit.